Mitigating Row Hammer Effect in 10-nm Node DRAM by Maximizing Word-Line Separation

초록

In this article, a reduced buried channel array transistor (R-BCAT) structure is proposed to mitigate the increasingly prominent row hammer (RH) effect, which is intensified by continued dynamic random access memory (DRAM) scaling. A maximized separation distance (SD) within a fixed word-line (WL) pitch leads to the suppression of capacitive crosstalk (CC) and trap-assisted electron migration (EM), improving RH immunity. R-BCAT represents the first architectural framework to achieve this maximization within existing DRAM design constraints. Chip-level measurements verified a notable reduction in RH-induced fail bits and stable DRAM functionality. In addition, the retention time (tRET) met the product specification. These results demonstrate the feasibility of a fabrication-compatible, device-level solution for improving RH robustness in scaled DRAM.

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