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초록

Heterogeneous integration of emerging two-dimensional (2D) materials with mature three-dimensional (3D) silicon-based semiconductor technology presents a promising approach for the future development of energy-efficient, function-rich nanoelectronic devices. In this study, we designed a mixed-dimensional junction structure in which a 2D monolayer (e.g., graphene, MoS2, and h-BN) is sandwiched between a metal (e.g., Ti, Au, and Pd) and a 3D semiconductor (e.g., p-Si) to investigate charge transport properties exclusively in an out-of-plane (OoP) direction. The role of 2D monolayers as either an OoP metal-to-semiconductor charge injection barrier or an OoP semiconductor-to-metal charge collection barrier was comparatively evaluated. Compared to monolayer graphene, monolayer MoS2 and h-BN effectively modulate OoP metal-to-semiconductor charge injection through a barrier tunneling effect. Their effective OoP resistance and resistivity were extracted using a resistors-in-series model. Intriguingly, when functioning as a semiconductor-to-metal charge collection barrier, all 2D monolayers become electronically "transparent" (close to zero resistance) when a high OoP voltage (greater than the built-in voltage) is applied. As a mixed-dimensional integrated diode, the Ti/MoS2/p-Si and Au/MoS2/p-Si configurations exhibit both high OoP rectification ratios (5.4 x 10(4)) and conductance (1.3 x 10(5) S/m(2)). Our work demonstrates the tunable OoP charge transport characteristics at a 2D/3D interface, suggesting the opportunity for 2D/3D heterogeneous integration, even with sub-1 nm thick 2D monolayers, to enhance modern Si-based electronic devices.

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