Low power consumption of non-volatile memory device by tunneling process engineering
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초록

Compared with Si3N4 and Al2O3, SiO2 grown using thermal oxidation process as tunneling layer has the advantages of high bandgap and well interface contact with the surface of silicon wafer, which can be a great solution to the leakage current problem of metal–insulator-semiconductor (MIS) devices. This study investigates the effect of improving the SiO2 tunnel layer on the operating voltage of MIS devices with a SiO2/HfAlOx/Al2O3 structure. The result shows the operating voltage changes as the tunneling layer thickness decreases, with a minimum of only 12 V for a 1.5 nm tunneling layer thickness. In addition, we found that pinholes are generated on the film surface when annealing a 1.5 nm SiO2 tunnel layer at 850 °C N2, in which case the operating voltage of the device is reduced to only 10 V, though it was also accompanied by the deterioration of the retention characteristics. © 2025 Elsevier Ltd

키워드

Charge trapping memoryElectrical characteristicsElectrical transportPinholeTunneling layer
제목
Low power consumption of non-volatile memory device by tunneling process engineering
저자
Wang, FuchengChu, MengmengChen, JingwenPan, ZhongKim, YongsangSong, Jang kunKhokhar, Muhammad QuddamahYi, Junsin
DOI
10.1016/j.sse.2025.109100
발행일
2025-06
유형
Article
저널명
Solid-State Electronics
226