A 1.2-V, 106.4-dB DR Discrete-Time Sigma-Delta Modulator with Feedback Adaptive Cascaded Integrator for Sensor Applications

초록

This innovative research work introduces a novel second-order discrete-time Sigma-Delta (ΣΔ) Analog-to Digital Converter (ADC) design for high performance signal conditioning sensors. A dual-phase noise rejection adaptive frequency gain (AFG) amplifier is designed with an output-stage CMFB circuit to ensure improved stability and performance. These circuits minimize flicker noise, refine noise shaping, and ensure precision, linearity, and stability. They enhance signal integrity, eliminate the need for high-gain amplifiers, and provide optimal loop gain, enabling an efficient modulator design. A highly efficient switched-capacitor feedback DAC enhances the loop filter’s input path. Switched-Capacitor feedback amplifier enables frequency-dependent gain control, signal integration, and differentiation, while miller compensation enhances stability and bandwidth. CMFB circuit is applied at the output of the AFG amplifier to enhance the power supply rejection ratio (PSRR). Low power dynamic latch comparator is used for high-speed, low offset, efficient noise performance and effective clock synchronization. A second-order discrete time modulator model was successfully fabricated using 0.13-μm CMOS technology. The structure exhibits an exceptional dynamic range (106.4dB) and 17.38-bit ENOB across 1.95 KHz bandwidth at 2 MHz sampling. The circuit consumes only 1.44 mW using 1.2 V supply. It occupies a minimal chip area of 0.14 mm2. © 2013 IEEE.

키워드