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초록

This paper presents a wide-range, fast-lock duty-cycle corrector (DCC) with a 5-bit successive-approximation register (SAR). An inverter-based bang-bang duty-cycle detector (BBDCD) is equalised before each comparison to suppress hysteresis, enabling deterministic decisions and a fixed 4-cycle per-bit schedule. The duty-cycle adjuster (DCA) uses a controller frequency code for range adjustment and applies delay equalisation to limit code-dependent delay during updates. A half-LSB post-bias then halves the SAR quantisation-error bound without extra cycles. Post-layout simulations in 28-nm CMOS show operation from 0.8 to 3.2 GHz over 38%-62% input duty with a 20-cycle lock, <= 1.0% maximum duty error, and 1.73 mW at 3.2 GHz.

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