SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters
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초록

Simultaneous multithreading (SMT) is widely used in modern x86 processors to improve core utilization by sharing hardware resources between co-located threads. However, such resource sharing often leads to severe performance interference, making efficient workload co-scheduling difficult, especially given the complexity and diversity of modern x86 CPUs. Our analysis reveals that SMT-aware workload scheduling can significantly improve system throughput and reduce tail latency for datacenter workloads, but identifying optimal thread combinations is challenging due to the lack of visibility into platform-specific resource sharing behaviors. In this paper, we present SMTcheck, a lightweight, accurate, and platformindependent methodology for predicting SMT interference for diverse x86 processors. SMTcheck uses carefully designed code snippets (Diags) to extract hidden microarchitectural features of performance-critical shared resources. With these extracted features, SMTcheck builds per-resource microbenchmarks (Injectors) to apply pinpoint pressure to specific target resources in order to capture workload-specific contention characteristics. SMTcheck then constructs a hardware-aware contention model to predict performance interference between arbitrary workload pairs without requiring exhaustive profiling. We evaluate SMTcheck on six x86 desktop processors and five x86 server processors from Intel and AMD across different generations and show that it achieves high prediction accuracy by up to 95.5% (94.6% on average). We further demonstrate its effectiveness by implementing a contention-aware scheduler in the Linux kernel. Compared to the default Linux scheduler, our contention-aware scheduler significantly reduces tail latency for latency-critical workloads (e.g., database, key-value store) by up to 36.09%, and improves the overall system throughput by up to 1.072 ×. Finally, using real-world cluster traces from Alibaba and Google, we demonstrate that SMTcheck incurs negligible profiling overheads (≈ 0.113%), making it practical for deployment in productionscale datacenter environments.

키워드

CharacterizationDatacenterMicroarchitectureScheduling
제목
SMTcheck: Accurate SMT Interference Prediction to Improve Scheduling Efficiency in Datacenters
저자
Kim, SanghyunOh, JinhyeokKim, TaehunKim, GyutaeKim, YoungsokHwang, JaehyunKim, Joonsung
DOI
10.1109/HPCA68181.2026.11408462
발행일
2026
유형
Conference Paper
저널명
IEEE High-Performance Computer Architecture Symposium Proceedings