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초록
As semiconductor scaling reaches the 1.4 nm node and beyond, extreme ultraviolet (EUV) lithography faces critical cost and physical constraints, particularly the tip-to-tip (T2T) spacing bottleneck. To address these challenges, we evaluate directional ion-beam etching (IBE) as a disruptive 3D patterning strategy to enable T2T shrinkage without additional EUV cut masks. We compare two distinct IBE architectures (that is, Grid and Ribbon Beam Systems) and it is found that, Ribbon Beam System showed better angle control characteristics and, for the Ribbon Beam System, precise angular control of the ion beam allows for a Y/X etch selectivity exceeding 10:1 in 42 nm back end of line (BEOL) patterns. This directional selectivity is further utilized to propose a novel 3D-IC interconnect strategy: tilted routing. By departing from traditional orthogonal coordinates and adopting diagonal routing paths inspired by IBE ion trajectories, we demonstrate the potential to eliminate up to four EUV-patterned layers (Via1/2, M2/3) in optimized logic structures. The feasibility of this approach has been validated on a 42 nm pitch BEOL pattern, confirming targeted critical dimension (CD) modulation and successful integration. From a manufacturing perspective, the proposed IBE-based integration can deliver a reduction of 30 auxiliary process steps, resulting in estimated cost savings of approximately 30 million per 10,000 wafers. These results establish IBEenabled tilted routing as a scalable and cost-effective solution for next-generation 3D-IC architectures, offering a viable pathway to extend scaling trends beyond the limits of conventional EUV lithography.
- 제목
- Ion Beam Etching as a Disruptive Integration Strategy for Advanced Logic: From T2T Scaling to Tilted 3D-IC Routing
- 저자
- Park, Jongsoon; Bai, Keun Hee; Ra, Hyonwook; Son, Seongho; Hong, Seongjun; Choi, Back Kyu; Kim, Sungtaek; Park, Yun Jae; Kim, Kyung Lim; Kim, Sunjung; Hong, Jong Woo; Kim, Sunghyun; Lee, Jong Myeong; Song, Jaihyuk; Park, Jongchul; Yeom, Geun Young
- 발행일
- 2026
- 유형
- Conference Paper
- 저널명
- 2026 Pan Pacific Strategic Electronics Symposium, Pan Pacific 2026
- 페이지
- 81 ~ 86