A 6.5-to-12.5Gb/s Reference-Less Dual-Loop CDR with Adaptive Injection Gain Switching and Self-aligned Injection Phase Detection in 28nm CMOS
  • Park, Minsu
  • Jin, Jahoon
  • Jung, Sangdon
  • Park, Hyunki
  • Chun, Jung-Hoon
Citations

SCOPUS

0

초록

Reference-less clock and data recovery (CDR) operates without an external clock, improving system efficiency [1]-[7]. Specifically, oversampling and injection methods are widely used for superior noise immunity in high-speed operations. These methods have been applied to enhance frequency-locked loops (FLLs) or phase-locked loops (PLLs). In studies on FLL ([2], [3]), the oversampling method was applied by rotating the sampling clock for frequency offset correction. However, under high jitter conditions, these designs are vulnerable to dead zones near data edges, compromising frequency offset detection accuracy. In studies on PLL ([4], [5]), the Injection method was applied to enhance loop bandwidth. But this approach requires precise delay line calibration to manage mismatches between the main and injection paths, adding design complexity.

제목
A 6.5-to-12.5Gb/s Reference-Less Dual-Loop CDR with Adaptive Injection Gain Switching and Self-aligned Injection Phase Detection in 28nm CMOS
저자
Park, MinsuJin, JahoonJung, SangdonPark, HyunkiChun, Jung-Hoon
DOI
10.1109/A-SSCC67472.2025.11349612
발행일
2025
유형
Conference Paper
저널명
2025 IEEE Asian Solid-State Circuits Conference, A-SSCC 2025 - Proceedings
페이지
286 ~ 288