ScholarWorks@성균관대학교

초록

Integrating ferroelectric Hf0.5Zr0.5O2 (HZO) into BEOL-compatible stacks requires strict Si-interface control under a low thermal budget. We compare wet chemical and dry thermal oxidation to form a SiO2 interfacial layer in Pt/Ti/HZO/SiO2/Si MFIS capacitors annealed at 300 °C. A dry-oxidized 1 nm SiO2 layer provides an atomically smooth template with a root-mean-square roughness of 0.082 nm, versus 0.253 nm for wet oxidation, enabling more uniform ALD growth and reducing oxygen vacancies in HZO from 7.0% to 4.0%. With Ti/Pt top-electrode confinement, the optimized stack exhibits strong ferroelectricity with a remnant polarization of 9.3 µC cm−2 and a current on/off ratio of about 190. Landau–Khalatnikov analysis shows that increasing the SiO2 thickness to 2 nm flattens the double-well potential and switches operation from hysteretic memory governed by transient negative capacitance to quasi-non-hysteretic logic governed by stabilized negative-capacitance-like behavior. transient time-domain measurements provide direct experimental evidence of Negative Capacitance (NC) dynamics, characterized by a voltage decrease simultaneous with a charge increase. These results provide a practical guideline for interface optimization and capacitance matching in HZO-based memory and steep-slope devices.

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