ScholarWorks@성균관대학교

초록

As dynamic random-Access memory (DRAM) devices continue to scale toward sub-10nm technology nodes, structural instability in Buried Channel Array Transistor (BCAT) architectures has emerged as a critical yield and reliability concern. In particular, high-Aspect-ratio word-line structures suffer from gate bending and wiggling phenomena during oxidation and metal deposition processes. These structural distortions lead to increased gate resistance, enhanced electric-field crowding, and elevated leakage currents, ultimately degrading refresh characteristics and data retention. In this work, we propose and experimentally validate two process-level solutions to mitigate BCAT patterning defects: (1) low-stress tungsten (W) gate metal through optimized boron incorporation, and (2) low-oxidation gate dielectric formation to suppress wiggling induced by silicon oxidation. Optimization of Ba Ha † flow rate and deposition conditions reduced BCAT gate bending by approximately 30%, while low-oxidation processing decreased wiggling severity by 17%. Electrical characterization confirmed improvements in word-line resistance and refresh performance. These results demonstrate that stress engineering and oxidation control provide practical and scalable solutions for enhancing BCAT structural integrity in advanced DRAM manufacturing.

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