ScholarWorks@성균관대학교

초록

Emerging transistors lack the statistical compact models needed to evaluate the yield of integrated circuits. To address this, we propose a novel framework combining a variational autoencoder (VAE) and an artificial neural network (ANN). Through the VAE method, a unique set of sources of unexpected process variations in I-V curves can be extracted. Furthermore, the latent vectors serve as inputs to an ANN-based compact model, which enables efficient Monte Carlo (MC) simulations. The proposed ANN-based statistical compact model was experimentally validated using fabricated roll-to-roll (R2R) printed single-walled carbon nanotube thin-film transistors (SWCNT TFTs). The model achieved greater than 98% fit accuracy on measured devices and greater than 90% similarity in key figures of merit (FoMs) in device-level statistical simulations. Our proposed model was implemented in Verilog-A and utilized in SPICE simulations. Our experimental results highlight the framework's adaptability and efficiency in handling unknown process variations. This data-driven approach for assessing the yield of emerging transistors has the potential to become a cornerstone of future design technology co-optimization (DTCO).

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