ScholarWorks@성균관대학교

초록

This article presents a selective dual shallow trench isolation (STI) oxide process as an effective solution to suppressing hot-electron-induced punch-through (HEIP) in advanced dynamic random access memory (DRAM) core pMOSFETs. The proposed process locally increases the STI sidewall oxide thickness to 250 & Aring; in the core region while maintaining the conventional SiO2/SiN stack in the cell region, thereby enhancing the lateral separation between the silicon channel and the trap-rich interface. Comprehensive reliability assessments under both dc and ac stress conditions demonstrate that the dual STI oxide architecture significantly improves device robustness. Notably, the off-state leakage current after prolonged ac stress is reduced by more than two orders of magnitude, and the ten-year lifetime voltage is enhanced by over 60%, compared with the conventional process. The dual-oxide structure effectively blocks hot-electron injection and suppresses trap-assisted punch-through, resulting in stable transfer characteristics, even under severe stress. Process integration studies confirm that the proposed approach maintains cell area efficiency and ensures cell gate fin uniformity. These results confirm that the dual STI oxide approach effectively mitigates HEIP-induced degradation without incurring a chip area penalty, thereby offering a scalable and manufacturable solution for improving the long-term reliability of next-generation DRAM devices.

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