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초록

This brief proposes a digitally calibrated two-point delta-sigma modulation scheme for CMOS RF transmitters aimed at Bluetooth Low Energy (BLE) systems. To compensate for gain mismatches between the VCO and DSM paths caused by process, voltage, and temperature (PVT) variations, this work utilizes an integrated frequency counter for digital calibration, thereby removing the dependency on additional analog circuitry. This approach ensures accurate frequency deviation while maintaining low area and power overhead. Implemented in a 55 nm CMOS process, the transmitter operates at 2.44 GHz with a 48 MHz reference, achieving ±250 kHz frequency deviation using a loop bandwidth of only 150 kHz. The chip occupies 0.28 mm2 and consumes 2.9 mW from a 1 V supply.

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