ScholarWorks@성균관대학교

초록

As DRAM devices encounter growing challenges from retention and disturbance errors, modern systems increasingly rely on frequent refresh operations to maintain data integrity. However, these additional refreshes introduce latency and degrade overall performance. We propose Hidden Refresh, a lowoverhead technique that issues refresh commands to idle rows during regular memory accesses, overlapping refresh with access operations. The mechanism requires only minor modifications to subarray decoders and no changes to the memory interface. Evaluations using gem5 on NPB and GAPBS benchmarks show up to 13.8% IPC improvements, demonstrating the scalability and efficiency of Hidden Refresh in mitigating refresh-induced overheads.

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