ScholarWorks@성균관대학교

초록

Conventional low-power flip-flops with reduced or no redundant transitions suffer from latency increase. To resolve the issue, this article proposes a low-power redundant transition-free flip-flop with reduced latency. It can reduce the latency by reconfiguring the primary stage to let it capture the input data directly. The proposed flip-flop can minimize dynamic power consumption by efficiently removing all redundant transitions. By adopting a full-static and contention-free structure, it can also provide robust operation. The proposed flip-flop was fabricated in a 28-nm CMOS process. The performance evaluation indicates that the proposed flip-flop achieves 26.0% and 21.5% DQ latency reductions from recent low-power flip-flops such as single-phase contention-free flip-flop (S ${<}^{>}\text{2}$ CFF) and REFF, respectively. It also indicates that the power consumption is reduced by 51.2% at 10% switching activity when compared with transmission-gate flip-flop (TGFF), a traditional primary-secondary flip-flop. Contributed by reduced latency and power consumption, the power-delay-product (PDP) of the proposed flip-flop is improved by 53.6%, 44.7%, and 17.1% when compared with TGFF, S ${<}^{>}\text{2}$ CFF, and REFF, respectively. The test of multiple dies having process, voltage, and temperature (PVT) variations indicates that the fully static and contention-free operation of the proposed flip-flop allows a reliable operation at a supply voltage down to 0.29 V without functional failure.

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