ScholarWorks@성균관대학교

초록

In this paper, we introduce a minimum-meansquared error (MMSE)-based crosstalk-aware equalizer design approach that enhances signal integrity (SI) in high-speed chiplet interconnects. Existing MMSE-based methods treat lanes in isolation or overlook inter-channel correlation, yielding suboptimal performance in densely routed high-speed links. By exploiting inter-channel correlations, our method computes feed-forward equalizer (FFE) tap weights that proactively suppress crosstalk and minimize interference-induced distortion. We validate our approach using a fast statistical eye simulator driven by a voltage-transfer-function (VTF) model, verified within 5% error against a commercial simulator. Evaluated on a 20-lane, 16 Gb/s/ lane interconnect, SI is improved by at least 21.2% versus standard MMSE, and outperforms crosstalk-aware MMSE variants by more than 8.6%. These results demonstrate that the proposed approach is a practical solution for designing robust, high-density chiplet interconnects.

키워드