@

초록

Probabilistic bit (p-bit) is the fundamental building block and core element of probabilistic computing (p-computing). However, physical separation of bit generation and memory storage creates a memory bottleneck in conventional p-computing architectures. We report on experimentally integrating voltage-tunable stochastic bit generation and non-volatile memory functionalities within a single in-memory device to realize a p-bit with van der Waals ferroelectric CuInP2S6 (CIPS). Leveraging the stochastic displacement of Cu+ ions and the material's remanent polarization under an external electric field, the proposed device achieves stable random bit retention (>1000 s) with low power consumption (similar to 75 nW). This eliminates the need for data transfer between separate memory and logic units, thereby enabling efficient in-memory p-computing with improved system-level performance. In-memory p-computing outperforms conventional p-computing in device-to-system-level NP-hard simulations, reducing time-complexity from O(n(2)) to O(n(1.5)). Notably, the sigmoid slope of the probabilistic output is dynamically tuned by varying the CIPS layer thickness, enabling adaptive control over exploration-exploitation characteristics. Broader slopes facilitate initial exploration, whereas steeper slopes support rapid convergence in later stages. Sigmoid slope tunability over a wide dynamic range (6.17-38.41) reduces convergence steps by 400-fold, highlighting the potential of CIPS-based p-bit as a compact, energy-efficient platform for scalable and adaptive p-computing.

키워드