ScholarWorks@성균관대학교

초록

In this paper, a D-band low-noise amplifier (LNA) using the linearity-enhanced technique in 40-nm CMOS process is presented. In this D-band LNA, multiple-gated transistors are used to improve the third-order intercept point (IIP3) while maintaining minimal small-signal gain reduction and nearly identical DC power consumption. This linearized LNA includes three conventional capacitive neutralization common-source differential stages and one multiple-gated transistor (MGTR) stage as the final stage. From the two-tone large-signal measurement results, the linear mode demonstrates a 5 dB improvement in the third-order intercept point (IIP3). In the one-tone large-signal measurement, a 4 dB improvement of the input 1-dB compression point (IP1dB) can be observed in the linear mode. For the small-signal measurement, this LNA achieves peak small-signal gains of 16.5 dB in normal mode and 14.2 dB in linear mode. The 3-dB bandwidth is 35 GHz (110-145 GHz) in both operating modes. Using the Y-factor method, the measured noise figure is 8.8 dB in normal mode and 9.5 dB in linear mode at 140 GHz. The DC consumption is 42 mW and 43 mW at 0.9 V for normal mode and linear mode. The whole chip area is 0.32 mm(2). To the author's knowledge, this is the first implementation of the MGTR technique in CMOS circuits operating beyond 100 GHz.

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