상세 보기
- Park, Geuntae;
- Han, Yuli;
- Yeo, Seongil;
- Kim, Jusung;
- Cho, Kunhee
SCOPUS
0초록
This paper presents a single-inductor multi-path multi-stage (MPMS) hybrid DC-DC converter designed for ultra-low voltage conversion ratio (VCR) operation. A design methodology for the inductor-middle hybrid converter architecture is introduced, and an optimized switched-capacitor (SC)-based hybrid converter for both the first and second stages, combined with the proposed multi-path (MP) design, is demonstrated. The MP architecture effectively reduces inductor RMS current and voltage stress on the switches, minimizing losses across a wide VIN range. A start-up control using only internal switches is also employed to pre-charge both the flying and output capacitors appropriately. The proposed MPMS hybrid converter is fabricated in a 0.18 μ m BCDMOS process and supports a Vin range of 9V-72 V and a Vout range of 1 V 2.2 V. A peak efficiency of 87.8% is achieved using a compact inductor with a 110 m Ω DCR.
키워드
- 제목
- A 9-72 V Input to 1-2.2V Output Single-Inductor Multipath Multi-Stage Hybrid Dc-Dc Converter Achieving 87.8% Peak Efficiency with 110m Ω DCR Inductor
- 저자
- Park, Geuntae; Han, Yuli; Yeo, Seongil; Kim, Jusung; Cho, Kunhee
- 발행일
- 2025
- 유형
- Conference Paper
- 저널명
- European Solid-State Circuits Conference
- 페이지
- 193 ~ 196