Repurposing Si CMOS nonidealities for stochastic and analog image processing

초록

Conventional semiconductor device engineering regards intrinsic device nonidealities as reliability concerns to be minimized or eliminated. Here, we demonstrate the strategic repurposing of these nonidealities as functional resources for advanced stochastic analog computing. We leverage two underutilized phenomena-deep-level channel trap-induced generation-recombination (G-R) noise and impact ionization-induced negative differential resistance (NDR) in body current-which have received limited attention compared to the extensively studied 1/f noise and monotonic drain current behavior in logic-centric transistors. By exploiting G-R noise with controllable temporal correlation and NDR with an unprecedented peak-to-valley ratio (2.78 × 104) within fully depleted silicon-on-insulator transistors fabricated in industry silicon complementary metal-oxide semiconductor (CMOS) process, we achieve multifunctional analog computation at the single-device level. Our transistor seamlessly performs stochastic encryption, deterministic signal readout, and analog inversion simply through reconfiguration of applied bias conditions, thereby eliminating the need for peripheral random-number generators, dedicated analog inverters, or amplifiers. This approach not only reveals the previously unrecognized computational potential embedded in mature CMOS technologies but also presents a scalable and energy-efficient alternative to architecture based on exotic materials, laying the foundation for next-generation analog computing systems.

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