ScholarWorks@성균관대학교

초록

In power management integrated circuits (PMICs) designed for low -voltage operation, particularly in mobile applications, overcoming the trade-off between on-state breakdown voltage (on-BY) and specific on-resistance (R-on,R-sp) in N -type power array CMOS remains a critical challenge. Conventional approaches, such as minimizing the distance to the P -body tap (P-tap), fall short in addressing the significant onBY degradation observed, especially in the central regions of the power array CMOS layout. This paper investigates additional systematic factors that influence local on -BV in power transistor structures. Through experimental data and simulations, we identify thermal disturbances and mechanical stress as primary contributors to BY degradation during full operation. To overcome these factors, we propose innovative layout engineering solutions, such as segmented centroid and stress -buffered P-tap designs. These low -risk and cost-effective solutions improve R-on,R-sp while maintaining a sufficient on -BY margin, all without requiring extra masks or process modifications.

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