ScholarWorks@성균관대학교

초록

Modern data-centric workloads are driving rapid growth in the demand for high-bandwidth, large-capacity memory. Compute Express Link (CXL) has emerged as a key technology for scalable memory expansion through the Peripheral Component Interconnect Express (PCIe)'s high-speed serial interfaces. However, while PCIe 6.0's L0p mode enables lane-level power gating without disrupting traffic flow, it lacks a policy mechanism for dynamically deciding the number of active lanes. Since actual energy savings depend on matching active lanes to runtime bandwidth demand, such a policy is essential. This paper presents DDLM (Demand-Aware Dynamic Link Width Management), a lightweight control framework that improves CXL link energy efficiency by dynamically adjusting link width based on runtime traffic. DDLM integrates two complementary modules: a predictor that predicts bandwidth demand based on short-term temporal locality to set the width ahead of hardware transition latency, and a congestion monitor that detects transient congestion via internal queue inspection. These modules are coordinated by a finite state machine that manages safe link width transitions under physical-layer constraints. We implement DDLM in the Ramulator2 simulator and evaluate it with diverse SPEC CPU workloads. Compared to a fixed-width baseline, DDLM reduces CXL Memory energy by up to 13%, improves utilization by 2.22x, and limits performance loss to under 3%. This work offers a practical path to energy-proportional CXL Memory.

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