Ferroelectric Tunnel Junction for CMOS-Compatible Low Power Neuromorphic SoC Applications: Modelling and Simulation Framework
  • Shin, Huiseong
  • Choi, Myeongjae
  • Lim, Subin
  • Han, Changwoo
  • Park, Hyeonjung
  • 외 2명
Citations

SCOPUS

0

초록

This work presents a compact modeling framework for FTJs using hafnia-based ferroelectrics for neuromorphic applications. FTJ behavior is modeled by integrating the Preisach polarization model with a non-local tunneling model based on the WKB approximation in Sentaurus TCAD. The impact of silicon doping on TER is analyzed, revealing that lower doping enhances resistance state contrast. Spike-based pulse modulation enables gradual polarization switching and multiple conductance levels. The model is validated through MNIST classification using TCAD-simulated data, demonstrating its potential for low-power, CMOS-compatible neuromorphic hardware.

키워드

FerroelectricFTJModellingNeuromorphic
제목
Ferroelectric Tunnel Junction for CMOS-Compatible Low Power Neuromorphic SoC Applications: Modelling and Simulation Framework
저자
Shin, HuiseongChoi, MyeongjaeLim, SubinHan, ChangwooPark, HyeonjungKim, JunseokShin, Changhwan
DOI
10.1109/ISOCC66390.2025.11329648
발행일
2025
유형
Conference Paper
저널명
International SoC Design Conference 2025, ISOCC 2025 - Proceedings of Technical Papers