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초록

As semiconductor systems scale toward higher performance and density, advanced packaging technologies must address both power integrity (PI) and thermal integrity (TI) challenges. Backside power delivery network (BSPDN) architectures reduce IR drop and improve layout flexibility, but they exacerbate thermal issues due to die thinning and backside metallization, resulting in tightly coupled PI-TI trade-offs. This paper proposes a reinforcement learning (RL)-based framework for BSPDN-aware co-optimization of floorplan and decap configurations, formulated using a deep Q-network (DQN). BSPDN-specific physical models, including a compact thermal resistance matrix and layout-constrained decap placement, are integrated for fast and accurate evaluation. The proposed method achieves more than 3.1% improvement in a scalarized figure of merit (FoM) over single-objective baselines, with over 90% runtime reduction. These results validate the effectiveness of the framework for scalable PI/TI co-design in BSPDN-integrated systems.

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