ScholarWorks@성균관대학교

초록

As processor microarchitecture is getting complicated, an accurate analytic model becomes crucial for exploring large processor design space within limited development time. An interval simulation is a widely used analytic model for processor designs in the early stage. However, it cannot accurately model modern microarchitecture, which has an unbalanced pipeline. In this work, we introduce IntervalSim++, an accurate analytic model for a modern microarchitecture design based on the interval simulation. We identify key components highly related to the unbalanced pipeline and propose new modeling techniques atop the interval simulation without incurring significant overheads. Our evaluations show IntervalSim++ accurately models a modern out-of-order processor with minimal overheads, showing 1% average CPI error and only 8.8% simulation time increase compared to the baseline interval simulation. © 2024 IEEE.

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