MOBO-Driven Advanced Sub-3-nm Device Optimization for Enhanced PDP Performance

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초록

Optimizing the nonlinear electrical characteristics of sub-3-nm devices requires considerable trial and error. However, due to the complexity of physics and secondary effects, technology computer-aided design (TCAD) simulations are time-consuming. Even with a combination of TCAD and a suitable design of experiments (DOEs), comprehensive exploration of the design space using TCAD is a challenging task. In this study, we propose a device optimization framework that can dramatically reduce the number of TCAD simulations while identifying the optimal device structure. The framework we propose consists of an artificial neural network (ANN)-based objective function derived from a dataset generated by weighted Sobol sampling, a multiobjective Bayesian optimization (MOBO) model for device optimization, and an ANN-based compact model for circuit simulation. The framework produced a device structure that showed a 51.5% performance improvement compared to the best device performance found from individual TCAD simulations of 128 structures. In contrast, the manual determination of a device achieving similar results required more than 2048 TCAD simulations. IEEE

키워드

Computational modelingData modelsIntegrated circuit modelingMachine learning (ML)OptimizationoptimizationPerformance evaluationsamplingSemiconductor device modelingSemiconductor process modelingSPICEsub-3-nm devicetechnology computer-aided design (TCAD)PARAMETERS
제목
MOBO-Driven Advanced Sub-3-nm Device Optimization for Enhanced PDP Performance
저자
Jeong, HyunJoonChoi, JinYoungCho, HyungMinWoo, SangMinKim, YohanKong, Jeong-TaekKim, SoYoung
DOI
10.1109/TED.2024.3378224
발행일
2024-05
유형
Article in press
저널명
IEEE Transactions on Electron Devices
71
5
페이지
2881 ~ 2887