A Balanced Shorted-Latch Sense Amplifier with PMOS Equalizer for Latency-Yield-Area Co-Optimization

초록

This paper proposes a balanced shorted-latch sense amplifier (SA) architecture that achieves simultaneous improvements in latency, sensing yield, and area efficiency. Conventional NMOS-based equalizer circuits in DRAM sense amplifiers often suffer from unbalanced drive strength and redundant transistor count, leading to higher mismatch and larger layout area. To address these limitations, the proposed PMOS-based equalizer replaces three NMOS devices with two PMOS transistors of identical width, simplifying the structure while maintaining the same functionality. Simulation results confirm a slight reduction in total sensing latency and improved sensing yield under threshold voltage variation, with reduction in equalizer transistor count. Although each metric shows modest enhancement, the overall design achieves a well-balanced improvement, providing a compact and stable sense amplifier suitable for advanced DRAM applications.

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