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초록

In this paper, we introduce a DRAM Error Correction Code (ECC) providing chipkill-level protection for x4 DDR5 DIMMs using 4-bit symbol Reed-Solomon (RS) codes. Since ECC was introduced to address increasing DRAM error rates caused by technology scaling, RS codes have been widely employed in various chipkill ECC solutions because of their robust burst error correction capability. Due to the limited codeword length of 4-bit symbol RS codes and mismatches with DDR4 DIMM configurations, 8-bit symbol RS codes have traditionally been preferred. However, the sub-channel configuration of DDR5 DIMMs is well-suited for 4-bit symbol RS codes, offering advantages such as reduced computational complexity and smaller lookup table (LUT) sizes owing to the decreased Galois field size. We propose a DRAM ECC scheme based on (10,8) 4-bit symbol RS codes and present comparative results evaluating its error correction and detection capabilities against existing ECC methods.

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