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초록

This article presents a high-resolution (HR) CMOS light detection and ranging (LiDAR) sensor capable of generating quarter video graphics array (QVGA) ( 320 & times; 240 ) depth images. To support high pixel density, the sensor employs a compact 6-transistor (6-T) nMOS-only single-photon avalanche diode (SPAD) analog front-end (AFE) with a column-shared active recharge circuit. A two-step histogramming time-to-digital converter (hTDC) with a priority memory (PM) architecture is proposed to minimize memory usage. The PM scheme dynamically allocates additional memory only to histogram bins with a high likelihood of containing signal echoes. As a result, the hTDC achieves a 51% memory reduction compared to conventional two-step implementations, requiring only 188 bits per channel. The sensor supports two pixel configurations: a merging mode, which combines eight SPADs to produce a 160 & times; 120 image with enhanced sensitivity, and an HR mode, which uses two SPADs per macro pixel to generate a full-resolution 320 & times; 240 image. The prototype chip was fabricated using a 110-nm back-side illuminated (BSI) CMOS image sensor (CIS) process. The prototype sensor generates depth images at 10 frames/s in HR mode and 40 frames/s in merging mode. Under 100 klx ambient light, the sensor demonstrates a worst case depth error of 5.7 cm and a depth precision of 0.2% at a distance of 42 m.

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