ScholarWorks@성균관대학교

초록

In this work, we present a novel approach using large pretrained models to generate compact models for semiconductor devices, accelerating design technology co-optimization (DTCO) in advanced technology nodes. Our pretrained models, initially trained on SPICE-generated planar MOSFET datasets, demonstrate strong adaptability to state-of-the-art logic technologies while maintaining high accuracy. By integrating these models with device-specific artificial neural networks (ANNs), we enable rapid compact model generation even with limited data. We validate our approach through DTCO analysis of vertically stacked nanosheet-based GAA-FETs, showing that it requires significantly fewer data points compared to conventional methods while enhancing both accuracy and simulation speed.

키워드