Improving Address Translation in Tagless DRAM Cache by Caching PTE Pages

초록

This paper proposes a novel caching mechanism for PTE pages to enhance the Tagless DRAM Cache architecture and improve address translation in large on-package DRAM caches. Existing OS-managed DRAM cache architectures have achieved significant performance improvements by focusing on efficient tag management. However, prior studies primarily update PTEs after caching data pages without directly accessing them from the DRAM cache, leading to performance degradation during page walks. To address this, we propose a method to simultaneously cache data pages and PTE pages in the DRAM cache. This approach reduces address translation latency and cache access delays. Additionally, we introduce a shootdown mechanism to maintain PTE and page walk cache consistency in multi-core systems, ensuring all cores access the latest information for shared pages. Experimental results show that caching PTE pages reduces address translation overhead by up to 33.3% compared to traditional OS-managed tagless DRAM caches, improving overall program execution time by an average of 10.5%. This method effectively mitigates bottlenecks caused by address translation.

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