A Fast-Converging Hybrid ZQ Calibration Architecture With Charge Injection for Multi-Die High-Density Memory Interfaces

초록

This article presents a fast-converging hybrid ZQ calibration architecture for multi-die high-density memory interfaces. In multi-die package systems, ZQ calibration latency increases because multiple dies share a single external reference resistor, making fast per-die calibration essential. To address this system-level challenge, the proposed architecture combines pre-driver voltage control for pull-up calibration with strength-code-based pull-down calibration, thereby reducing loop count and routing complexity while minimizing calibration time and chip area. In addition, shared reference loading increases the effective capacitance at the ZQ node, degrading voltage transition speed and limiting the operating frequency of the ZQ loop. To mitigate this physical limitation, a ZQ charge injection equalizer accelerates the node transition, achieving up to 95.6% improvement in the maximum operating frequency of the ZQ loop under 32-load conditions based on post-layout simulations. Furthermore, a reference-voltage-switching-based offset cancellation scheme removes comparator offset within 2 ZQ clock cycles, thereby minimizing calibration time overhead while enhancing calibration accuracy and statistical consistency across chips. Fabricated in a 28-nm CMOS process, the circuit operates at 1.0 V/1.8 V (V(CC)Q/V-CC), occupies 0.0303 mm2, and achieves 160 ns calibration time at 100 MHz with a maximum error of 3.9 mV across 20 measured chips.

키워드