ScholarWorks@성균관대학교

초록

Data-intensive applications access large address spaces and exhibit low locality when accessing virtual addresses (VA). The level 2 translation lookaside buffer (L2 TLB) misses trigger page table walks (PTWs), and the PTWs become a bottleneck, requiring up to five memory accesses for address translation. Among four page caches used to reduce memory accesses during PTWs, the page directory entry cache (PDE cache) experiences the highest number of miss counts. In addition, the L2 TLB indicates an underutilized characteristic with a low reuse count of L2 TLB entries. The study proposes an architecture that stores PDE cache entries in the L2 TLB, leveraging the underutilized property of the L2 TLB and the strain on the PDE cache. The expansion of the PDE cache storage space results in a diminution of memory accesses during PTWs, leading to enhanced performance in data-intensive applications. Even with the reduced L2 TLB capacity, the impact on performance degradation is minimal since the reduction affects the space occupied by underutilized entries. The proposed architecture demonstrates a 76.77% decrease in average memory access counts during PTWs and a 6.41% improvement in average instructions per cycle (IPC). © 2025 IEEE.

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