Sliding-Block DFE Error Propagation Correction under Uncertainty with Reverse-Decision Evaluation for High-Speed Wireline Receiver on FPGA
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초록

This brief presents a PAM-4 sliding-block decision feedback equalizer (SB-DFE) employing the correction under uncertainty with reverse-decision evaluation (CURE) scheme. Conventional SB-DFE resolves timing bottlenecks in high-tap DFE by breaking the feedback loop, but remains vulnerable to intra-block error propagation. To address this, the CURE scheme is integrated for localized sequence estimation, which conditionally evaluates candidate sequences prompted by unreliable decisions to suppress error propagation with minimal complexity. Leveraging the SB-DFE structure to compensate for long-tail post-cursor intersymbol interference enables the use of a shortened feed-forward equalizer (FFE). This provides a higher signal-to-noise ratio for CURE than 4-state maximum likelihood sequence detection (MLSD), as the latter suffers from noise amplification in its longer FFE. Field-programmable gate array-based link emulation confirms the proposed architecture outperforms 4-state MLSD across various noise conditions. ASIC synthesis in a 28-nm FD-SOI technology further confirms that the design reduces area and power by 2.90× and 4.05×, respectively, relative to the MLSD benchmark.

키워드

Decision feedback equalizer (DFE)digital signal processing (DSP)error propagationfield-programmable gate array (FPGA)four-level pulse amplitude modulation (PAM-4)maximum-likelihood sequence detection (MLSD)sliding-block DFE (SB-DFE)
제목
Sliding-Block DFE Error Propagation Correction under Uncertainty with Reverse-Decision Evaluation for High-Speed Wireline Receiver on FPGA
저자
Park, Se-UngLee, JunyeongChoi, JaeminChun, Jung-Hoon
DOI
10.1109/TCSII.2026.3679301
발행일
2026-05
유형
Article
저널명
IEEE Transactions on Circuits and Systems II: Express Briefs
73
5
페이지
563 ~ 567